DS1302 timekeeping chip


The DS1302 trickle-charge timekeeping chip contains a real-time clock/calendar. Also it includes 31 bytes of battery-backed general-purpose static RAM. It communicates with a microprocessor via a simple serial interface. The real-time clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator.
Interfacing the DS1302 with a microprocessor is simplified by using synchronous serial commu-nication. Only three wires are required to communicate with the clock/RAM which are: CE, I/O (data line), and SCLK (serial clock). Data can be transferred to and from the clock/RAM 1 byte at a time or in a burst of up to 31 bytes. The DS1302 is designed to operate on very low power and retain data and clock information on less than 1µW.


(Pin1 Vcc2) Primary Power-Supply.
(Pin2 and Pin3, X1 and X2) Connections for Standard 32.768kHz Quartz Crystal.
(Pin4 GND) Ground.
(Pin 5, CE) Input. CE signal must be asserted high during a read or a write. This pin has an inter-nal 40kΩ (typ) pulldown resistor to ground.
(Pin6 I/O) Input/Push-Pull Output. The I/O pin is the bidirectional data pin for the 3-wire inter-face. This pin has an internal 40kΩ (typ) pulldown resistor to ground.
(Pin7 SCLK) Input. SCLK is used to synchronize data movement on the serial interface. This pin has an internal 40kΩ (typ) pulldown resistor to ground.
(Pin8 Vcc1) In systems using the trickle charger, the rechargeable energy source is connected to this pin. VCC1 is connected to a backup source to maintain the time and date in the absence of primary power. The DS1302 operates from the larger of VCC1 or VCC2. When VCC2 is greater than VCC1 +0.2V, VCC2 powers the DS1302. When VCC2 is less than VCC1, VCC1 powers the DS1302.


The DS1302 uses an external 32.768kHz crystal. The oscillator circuit does not require any ex-ternal resistors or capacitors to operate.
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error will be added by crystal frequency drift caused by temper-ature shifts. External circuit noise coupled into the oscillator circuit may result in the clock run-ning fast


Figure shows the command byte. A command byte initiates each data transfer. The MSB (bit 7) must be a logic 1. If it is 0, writes to the DS1302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits 1 to 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0).


Driving the CE input high initiates all data transfers. The CE turns on the control logic that al-lows access to the shift register for the address/command sequence. The CE signal provides a method of terminating either single-byte or multiple-byte CE data transfer.
A clock cycle is a sequence of a rising edge followed by a falling edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. If the CE input is low, all data transfer terminates and the I/O pin goes to a high-impedance state. Figure shows data transfer. At power-up, CE must be a logic 0 until VCC > 2.0V. Also, SCLK must be at a logic 0 when CE is driven to a logic 1 state.


Following the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored should they in-advertently occur. Data is input starting with bit 0.


Following the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur so long as CE remains high. This operation permits continuous burst mode read capability. Also, the I/O pin is tri- stated upon each rising edge of SCLK. Data is output starting with bit 0.


Burst mode can be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (we set address/command bits 1 through 5 = logic 1). As before, bit 6 speci-fies clock or RAM and bit 0 specifies read or write. For more information see DS1302’s datasheet.


The time and calendar information is obtained by reading the appropriate register bytes. Table 3 illustrates the RTC registers. The time and calendar are set or initialized by writing the appropri-ate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format.
The following Table 3 illustrates the RTC registers. The first column READ of the Table corre-sponds to the hexadecimal representation or the command byte which defines the particular reg-ister of DS1302 in reading mode. The column WRITE of the same Table is referred to the com-mand byte which corresponds to the same register in writing mode. For reading the LSB of command byte must be logic 1 while for writing the LSB of command byte must be logic 0.

The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries result in undefined operation.
When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buff-ers are synchronized to the internal registers the rising edge of CE.
The countdown chain is reset whenever the seconds register is written. Write transfers occur on the falling edge of CE. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within 1 second.
The DS1302 can be run in either 12-hour or 24-hour mode. Bit 7 of the hours register is defined as the 12- or 24- hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). The hours data must be re-initialized whenever the 12/24 bit is changed.


Bit 7 of the seconds register is defined as the clock halt (CH) flag. When this bit is set to logic 1, the clock oscillator is stopped and the DS1302 is placed into a low-power standby mode with a current drain of less than 100nA. When this bit is written to logic 0, the clock will start. The ini-tial power-on state is not defined.


Bit 7 of the control register is the write-protect bit. The first seven bits (bits 0 to 6) are forced to 0 and always read 0 when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high, the write-protect bit prevents a write operation to any other register. The initial pow-er-on state is not defined. Therefore, the WP bit should be cleared before attempting to write to the device.


This register controls the trickle-charge characteristics of the DS1302. For more information see DS1302’s datasheet.


The static RAM is 31 x 8 bytes addressed consecutively in the RAM address space.